Semester : SEMESTER 6
Subject : VLSI
Year : 2019
Term : MAY
Branch : ELECTRONICS & COMMUNICATION ENGINEERING
Scheme : 2015 Full Time
Course Code : EC 304
Page:2
F1034 Pages: 2for worst-case delay.b) Explain 4x4 bit-array multiplier with block diagram. (10)wRPage 2 of 2