9 a)

b)

00000EC207121901

Draw the state diagram and design a 3 bit up/down binary counter comprises a
clocked sequential circuit having a level control input x and a clock input. It is
required that when x = 0 the counter counts up and when x = | the counter counts
down.
Reduce the given state table using implication chart and obtain the equivalent
states

Present state

ணை

8... | > | 0

© F E 0 | 0 |
0. | ட ற. | F 0 | 0 |
E | 28 | G 09 |
F G 0 0 | 1
G A F | 0 | | 0 |

aK

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