APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Previous Years Question Paper & Answer

Course : B.Tech

Semester : SEMESTER 4

Year : 2018

Term : APRIL

Scheme : 2015 Full Time

Course Code : CS 202

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B4810 Pages: 2

The cache block size in many computers is in the range of 32 to 128 bytes.
What would be the main advantages and disadvantages of making the size of
cache blocks larger?

What is flash memory?

PART D
Answer any two questions, each carries 9 marks

With a diagram, explain the PCI bus.

Write a note on the packet type formats of USB.

What are interrupts? List the sequence of steps following an interrupt request.
Describe semiconductor RAM memories.

With the help of an example, explain the different cache mapping function

A computer system has a main memory consisting of 1M 16-bit words. It also
has a 4K-word cache organized in the block-set-associative manner, with 4
blocks per set and 64 words per block. Calculate the number of bits in each of
the Tag, Set, and Word fields.

PART E
Answer any four questions, each carries 10 marks

Discuss shift and conditional control micro operations.

An 8-bit register A has one input x. The register operation is represented
symbolically ೩5 P: 07 — x, Aj — Ais) 1 = 0,1,2,3 ... 6. What is the function of
the register?

Compare vertical and horizontal microinstruction formats, giving examples.

With a diagram, explain how control signals are generated using hardwired
control.
Describe the purpose of microprogram sequencing. How is it carried out?

Draw the block diagram for the hardware that implements the following
statement x + yz: AR > AR + BR where AR and BR are two n-bit
registers and x, y, and z are control variables. Include the logic gates for the
control function. (The symbol + designates an OR operation in a control or
Boolean function and an arithmetic plus in a micro operation.)

Explain the design of status register.

اد ‎೫‏ ید اد

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