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G192056 Pages:3

dependency graph. Also detect the parallelism embedded in them.

51 : Load 1൪ ,M(100) 7/11 < Memory(100) /

52 : Move 1२2 , 1२1 /1२2 «- (२1 )/
93 : 10௦1 181 <~ (२1 )+ 1/
54: Add 1२2 , 1२1 / २2 <~ (२2 ) + (1१1) /

95 : Store M(100),R1 7 Memory(100) ൦ (२1) /
Define the inclusion property of a memory hierarchy. Illustrate the data transfers

between adjacent levels of a memory hierarchy.

Consider a two-level memory hierarchy, M1 and M2 of sizes 64Kbytes and
4Mbyftes respectively, with access time [1 = 20ns and (2 = 200ns and costs cl and
௦2 are $0.01/byte, ௦2 = $0.0005/byte respectively. The cache hit ratio hl = 0.95 at
the first level. Find the effective access time and total cost of this memory system.
Differentiate between the following with necessary diagrams:

UMA and NUMA multiprocessor models.

RISC and CISC

PART C
Answer any two full questions, each carries 9 marks.
Explain the different levels of hierarchy of bus systems.

Define the write-invalidate snoopy bus protocol for maintaining cache coherence.
Show the different possible state transitions for write-through and write-back cache
using the write-invalidate protocol.

Consider the five-stage pipelined processor specified by the following reservation
table and answer the following: (S indicate the stages)

1 2 3 ந்தி 5 ந்த
51 × ×
52 × ×
53 X
54 X X

(i) List the set of forbidden latencies and the collision vector.
(ii) Draw the state transition diagram showing all possible initial sequences without

causing a collision in the pipeline.

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