Cc G192056 Pages:3

Reg No.: Name:

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
SEVENTH SEMESTER B.TECH DEGREE EXAMINATION(R&S), DECEMBER 2019
Course Code: CS405
Course Name: COMPUTER SYSTEM ARCHITECTURE

Max. Marks: 100 Duration: 3 Hours
PARTA
Answer all questions, each carries 4 marks. Marks
1 A 4003187 processor was used to execute a program with 150000 floating point (4)

instructions with clock cycle count of 1. Determine the execution time and MIPS

rate for this program.
2 State Amdahl’s law. Write an expression for the overall speed up. (4)
3 Distinguish between scalar RISC and super-scalar RISC in terms of instruction (4)

issue, pipeline architecture and performance.

4 Discuss the schematic representation of a generalized multiprocessor system. (4)
5 Explain chained cache coherence protocol. (4)
6 Consider the execution of a program of 15,00,000 instructions by a linear pipeline (4)

processor with a clock rate of 1000 MHz. Assume that the instruction pipeline has
five stages and that one instruction is issued per cycle. The penalties due to branch
instruction and out-of-order execution are ignored.
a) Calculate the speedup factor in using this pipeline to execute the program as
compared with the use of an equivalent non-pipelined processor with an
equal amount of flow-through delay.

b) Find out the efficiency and throughput of this pipelined processor.

7 Write short notes on internal data forwarding. (4)
8 Explain Goodman’s write once protocol with transition diagram. (4)
9 List any two advantages and disadvantages of Scalable Coherence Interface(SCI). (4)
10 What are the four context switching policies adopted by multithreaded (4)

architectures?

PART B
Answer any two full questions, each carries 9 marks.

11 8) Discuss the Bernstein’s conditions for checking the parallelism among a set of (3)

processes.

b) Analyze the data dependences among the following statements and construct a (6)

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