E B3E011S Pages: 3

Reg. No. Name:
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
THIRD SEMESTER B.TECH DEGREE EXAMINATION, JULY 2017

Course Code: EC 207
Course Name: LOGIC CIRCUIT DESIGN (AE, EC)

Max. Marks: 100 Duration: 3 Hours
PARTA
Answer two questions, Question no. 3 is compulsory.
1. a) Convert the first twelve integers into Binary, Grey and BCD. (4)
b) Perform the following operations [show the intermediate steps]. (6)

i) 5743)8 —3672)s

ii) CFD4)i6—6A51)i6

iii) 56)10 - 48)10 using 2’s and 1’s complement method
iv) 316.645) ம into Binary, Octal and Hexadecimal

€) What is Hamming code? How is the Hamming code word tested and corrected.
Encode the data bits “1101” into the 7-bit even parity Hamming code. (5)
2. a) Show how four single bit full adders can be combined to implement a four bit

ripple carry adder. Design and realize a four bit adder/subtract circuit using the four
bit adder block and logic gates. The add/subtract function can be selected by using
a control signal. Justify your answer with at least one example from each category.
(5)
b) For the Boolean function ۶ = A.B.C+A.C.D+A.C.D+B.C.D+B.C.D.
Show how it can be implemented using i) One 16:1 multiplexer ii) One 8:1
multiplexer and one or more NOT gates. (10)

3. a) Ina computer system, numbers are represented using words with a length of 4
bits.
(i) What is the range of positive numbers that can be represented using unsigned
binary numbers?
(ii) Explain how the 1’s and 2’s complement representation can be used to describe
signed binary numbers.
(iii) Prepare a table showing all the positive and negative numbers which can be
represented using 4 bit words in “sign magnitude”, “15 complement” and “25
complement” representation and mark the maximum and minimum in each case. (8)
b) Design and realize a 8:3 priority encoder. (7)

PART B
Answer two questions, Question no. 6 is compulsory.
4. a) Define the terms noise margin, voltage and current levels, propagation delay, fan
out and power dissipation related to a logic families. Prepare a comparison table
showing the values of each for the TTL, ECL and CMOS logic families. (6)

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