APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Previous Years Question Paper & Answer

Course : B.Tech

Semester : SEMESTER 5

Year : 2017

Term : DECEMBER

Scheme : 2015 Full Time

Course Code : EC 361

Page:3





PDF Text (Beta):

F7196
Draw and explain the architecture of Xilinx 9500-family CPLDs. Also explain the
function block architecture.
Describe the different test generation techniques for PLA.
Explain the internal structure of an XC4000-series CLB.
Explain different testable PLA Designs.

Using suitable illustrations explain the XC4000 programmable interconnect.
‏اد عد اد اد‎

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