Semester : SEMESTER 5
Subject : Digital System Design
Year : 2017
Term : DECEMBER
Scheme : 2015 Full Time
Course Code : EC 361
Page:3
F7196
Draw and explain the architecture of Xilinx 9500-family CPLDs. Also explain the
function block architecture.
Describe the different test generation techniques for PLA.
Explain the internal structure of an XC4000-series CLB.
Explain different testable PLA Designs.
Using suitable illustrations explain the XC4000 programmable interconnect.
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