6)

7)

8)

9)

a)
b)

a)
b)

a)
b)

a)
b)

Distinguish between synchronous and asynchronous sequential circuits. 4.5
Explain the routing structures available on an FPGA. 4.5
PART C
Construction of an SM chart for the control network of binary divider. 6
Describe operator overloading and enumerated data types in VHDL with
examples. 6
Explain different part of an SM chart. 6
Explain procedure call in VHDL with example? Write down a function capable of
converting integer to 510) LOGIC VECTOR. 6

What is an SM chart? How will you convert state diagram to an SM chart. 6
Differentiate various styles of modeling in VHDL. 6