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06000EE365122001

Write and explain the VHDL code for an n bit binary up counter.
Write the VHDL model for SIPO right shift register.
Explain the steps involved in design of a (synchronous sequential) digital
system.
Explain how a ROM chip is modelled using VHDL.
PART 0

Answer any two full questions, each carries 10 marks.
Explain simulation cycle of VHDL and its phases.
Explain the main component of IEEE .1149.1 boundary scan test architecture.
Explain built in self-test scheme.

Explain compilation and elaboration process in VHDL.

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