Semester : SEMESTER 3
Subject : Logic Circuit Design
Year : 2020
Term : SEPTEMBER
Scheme : 2015 Full Time
Course Code : EC 207
Page:3
00000EC207121904
9 a) Draw the state diagram, state transition table and state equation using D flip flop (10)
for the given state table.
A । B | 0 |
< | B | o | 0 |
है {| «م | o | 0 |
11)
0) Design a synchronous counter using T flipflop to count the following sequence. (10)
0-3-1-4-6-0
RE
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