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ADD R6.R8.R5
(6)
b) Illustrate the use of Vector Mask Registers Vector architecture. (3)
5. a) Explain the concept of Branch Target Buffer.
b) Write notes on the following
i) ISA of intel core-i7
ii) Pipelining in intel core-i7 (6)
6. a) Discuss about ILP Wall
b) Compare Vector architecture and GPU (4)
Part C (Each Question Carries 12 Marks)
7. a) Draw the switch settings of an 848 Omega network built with 2x2 switches for the permutation
(0,502). Explain the routing of a message from input 110 to 100 (6)
b) Discuss directory based cache coherence protocol (6)
8. a) Compare C-Access and S-Access memory schemes. (6)
b) Explain Snooping based cache coherence protocol (6)

9. a) What do you understand by blocking and non-blocking switching networks

b) Discuss distributed and shared memory system in Multiprocessor architecture (6)