Semester : SEMESTER 1
Subject : DSP System Design
Year : 2017
Term : DECEMBER
Branch : SIGNAL PROCESSING
Scheme : 2015 Full Time
Course Code : 01 EC 6307
Page:1
No. of Pages:3
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FIRST SEMESTER M.TECH DEGREE EXAMINATION, DECEMBER 201 7
Electronics & Communication Engineering
Signal Processing
01 EC6307 DSP System Design.
Answer any two full questions from each part Limit
answers to the required points.
Max. Marks: 60 Duration: 3 hours
PART A
1. 8. Give the method to reduce the size of ROM by offset coding in Distributed (4)
Arithmetic.
b. Consider the RNS (8/7/5/3) (5)
i) Represent the numbers x= 128 and 35 in this RNS ii)
Convert (3/2/4/2) into decimal iii) Compute x+y, x-y
2. a. Consider a prime moduli p=17 , generator 2-3 will generate the elements of a (4) finite
field. Compute a x b and a + b in index domain (௨3, b=2)
Encoding table is given below.
0123 5 fi $910 121.3 15 :لآ
inda(a) عد- 14 12515 10'237 13.19 6 8
உ ومس 012394567 8 9 10 11 12 13 14 4446466 ್ಪ
2) 0 14 12 3 7 9 15 8 13 -० 6 2 10 5 4 1 11
b. Give the basic features that must be provided in DSP architecture to implement (5)
convolution operation.
3. a. Derive the equations required for the implementation of CORDIC algorithm. (൭)
Using this, compute sin (60) and cos (60) to a precision of 4 bits.
b. How can the 9 bit LNS coding 000111.0010 (radix 2, 2 sign bits, 3 bits for integer
(3) precision, 4 bit fractional precision)be translated into real number system ?
PART B
4. 2. Mention the performance issues in pipelining. Give the performance of pipeline (4)
with stalls.