MODULE V & MODULE VI

7. a)Assume a computer where the CPI is 1.0 when all memory accesses hit in the
cache. The only data accesses are loads and stores, and these total 50% of the
instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how

much faster would the computer if all instructions were cache hits? (6)
b) Give any three optimization techniques to improve cache performance (6)
8. a) Explain the limitations of ILP (6)

b) Explain the features of code composer studio of TMS 320C 6713 Processor (6)

9) a) Explain the memory architecture of [MS 3207 6713 Processor. (6)
b) Write an assembly language program to implement Yn=1a(n). x(n)(6)