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ஆ “INTERRUPT SERVICING (HANDLING) MECHANISM

m has an interrupt servicing (handling) mechanism. The OS also
‏فوع‎ மிருத (Section 8.7).

ks interrupt Vector

vector 15 ೩ memory address to which the processor vectors. The processor transfers the program

to the interrupt vector new address on an interrupt. Using this address, the processor services that

काणा bY executing corresponding ISR. The memory addresses for vectoring by the processor are processor-

of microcontroller-specific. Vectoring is as per the provisions in interrupt-handling mechanism. The various
mechanisms are as follows:

Vectoring to the ISR_ VECTADDR = On an interrupt, a processor vectors to a new address,
98 VECTADDR. It means that the PC (program counter), which has the instruction address of next instruction,
saves that address on stack or in some CPU register, called link register and the processor loads the
ISR_VECTADDR into the PC. The stack pointer register of CPU provides the saved address to enable
return from the ISR using the stack. When the PC saves at the link register it is part of the CPU register set.
Section 4.6 will explain the mechanism for saving the CPU registers in detail. The [SR last instruction is RETI
(return from interrupt) instruction.

provides tor mechanism for