0 0800CST203122001 Pages: 2

Reg No.: Name:
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Third Semester B.Tech Degree Examination December 2020 (2019 Scheme)

Course Code: CST203
Course Name: LOGIC SYSTEM DESIGN

Max. Marks: 100 Duration: 3 Hours
PARTA
Answer all questions. Each question carries 3 marks Marks
1 Convert (456.78) to a) binary 0) octal and 0) hexadecimal (3)
2 Write a) 1’s complement and 2) 2’s complement representations of (-126) (3)
3 State and prove De Morgan’s Theorem (3)
4 Design a circuit using NAND gates for implementing EXCLUSIVE-OR (3)
function
ട്‌ Design a half adder circuit using any universal gate. (3)
6 Draw the logic diagram of a 2x1 multiplexer circuit (3)
7 Derive the characteristic equation of a D flip flop from its excitation table. (3)
8 How is a sequential circuit different from a combinational circuit? Give an (3)
example for each circuit.
9 Distinguish between a ring counter and Johnson counter (3)

10 When do you implement a combinational circuit using ROM and when do (3)
implement a combinational circuit using PLA in preference to ROM.

Answer any one full question from cach module Each question carries 14 marks
Module 1
11 a) Convert 1) (13AF)j¢ to octal ii) (10110101.101) to decimal (6)
b) Add 1) BCD numbers 1567 and 968 ii) octal numbers 2376 and 5677 (8)
12 a) Perform the following operations using 2’s complement representation (10)
i) (-34) + (+21) 1) (+26) - (-12) iii) (-33) + (-22) iv) (445) - (432)
b) Convert i) (10011010) in 2’s complement form to decimal (4)
ii) (10111001) in 1’s complement form to decimal
Module 2
13 a) Using K Map simplify the function (8)
F(w, x. 9, 2) = 2 (0,1,2,3,5,7,8,9,10,13,15)
b) Express the above function in product of maxterms form. (6)

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