Semester : SEMESTER 5
Subject : VLSI Circuit Design
Year : 2020
Term : DECEMBER
Scheme : 2015 Full Time
Course Code : AE 363
Page:2
0000030112103
Explain the clocked sequential circuit of JK and SR flipflop.
Explain the scaling models and scaling factors for device parameters.
Explain the dual rail coding used in signal generate completion signal.
Explain the problem of skew and jitter.
Explain arbiters.
KK KKK
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