Semester : SEMESTER 3
Subject : Switching Theory and Logic Design
Year : 2017
Term : DECEMBER
Branch : COMPUTER SCIENCE AND ENGINEERING
Scheme : 2015 Full Time
Course Code : CS 203
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C7113
PART D
Answer any two full questions, each carries 9 marks.
Design a 4-bit Binary to Gray code converter.
Implement the logic function F = 4 ಈ 8 © using 2 8:1 multiplexer.
Explain race around condition in JK flip-flop. Explain how a master slave flip-
flop avoids race around condition.
Convert JK Flip-Flop to T Flip-Flop.
Design and implement full subtractor by using only NAND gates.
Explain 2 bit magnitude comparator using logic diagram.
PART E
Answer any four full questions, each carries 10 marks.
Design a synchronous counter using JK flip-flop which counts through the
states 0,1,3,4,5,6,0...... Is the counter self starting?
Draw and explain 4 bit Johnson counter. Also draw its timing sequence.
Draw and explain the different types of shift registers.
List down the applications of shift registers.
Write short notes on PLA.
Give any 2 applications of ROM.
Compare Static RAM and Dynamic RAM.
Find the minimum size of PLA required to implement the following functions?
Hence implement the following function using PLA.
F,(A,B,C) = ¥m(0,2,4,7) 7} (4, B,C) = ¥m(3,5,6,7)
Explain the algorithm for floating point addition and subtraction.
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