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02000EC206052004

PART (^

Answer any two full questions, each carries 20 marks
Explain any two modes of data transfer between the processor/memory and I/O
devices in a computer system.
Draw the internal organization of a DRAM cell and explain the read and write
operation.
Illustrate virtual address to physical address translation using page table.
Define miss rate and average memory access time.
Draw the internal organization of a SRAM cell and explain the read and write
operation.
Compute the size of a 4096-word x 32-bit memory array. Also find the width of
address and data bus.
Describe temporal locality and spatial locality with respect to cache memory.
Illustrate how data is found in a C=8 word, 2-way set associative cache

Draw the internal organization of a 4 x 3 memory array.

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