b. Explain how RAW hazards are resolved in the basic Tomasulo's algorithm. (5)

5. 9. Draw the datapath for handling conditional branching instructions in MIPS. (5)
Also explain the various steps in the execution of a conditional branching instruction
in 8 5 stage pipelined processor.

b. Identify all data dependencies in the following code, assuming that we are using (4)
the 5-stage MIPS pipelined datapath. VVhich dependencies can be resolved via
forwarding? http:/ftvww.ktuonline.com
೨೫2,೫೩5,7೫4 ‏ممم‎
‎೨ R4,R2,R5
R5,100(R2)
2 R3,R2,R4

ADD

SW

ADD
6. a. With an example explain load use data hazard. How it can be eltininated?

b. Differentiate hazard and dependency (2) Identify the type of data hazards (3)

i) add SSI, $s2, $s3 mul

SsO,
3 lw $s1,0($s2)

501) 244 ‏.ہ0‎
‎7 sw $s1,0($t0)
॥) add $s1,$s0,$t1

PART C

7. a. Give the limitations of Instruction level parallelism. (2)

b. With proper examples, explain the difference between linear and circular (5)
addressing modes in C 6713 processor. Specify the applications in which these
addressing modes are used.

c. Explain the various dynamic branch prediction schemes.

8. a. Assuming a cache of 4K blocks, a two word block size and a 32 bit address, find (6)

total number of sets and total number of tag bits for cache that are direct mapped, 2
way , 4 way set associative and fully associative.

2
b. Briefly explain the features of a TMS 320C6713 processor.

9. a. Which has tower miss rate: a 16KB instruction cache with a 16KB data cache (6)
or a 32KB unified cache? (Assume 36% of the instructions are data transfer