⋅⋅⋯ ⋅≤≳↿↘ ⋅ جا
‎Bulk ter and then release of the 10‏ 1111( ہہت ‎pol on the system bus only after the transfer is‏

{8.1 use of DMAC

೩ DMA request 15 made to the DNV ‘Os
le write. (ii) mode (bytes, burst sar ee the 10൦. the DMAC is first initialized. It is programmed
எம்‌ क 3 mae of DMA wansfer, (iii) total number of bytes to be transferred
pi — ‏نے 906 سے‎ oom ண ead Operation (extemal device to memory transfer). DMA
ಸ ‏شی ہے‎ vera DMA ‏تو‎ २4 (1) at the start of DMAC programming and initializing
od (४) one ‏نم وی اج‎ request by the external device is made to the DMAC, the CPU is
कि 1 ۲ DMAC at the start to initiate the DMA and at the end to notify the end of the
DMA by DMAC. Example 4.16 explains the data transfer operation. ∎

gxomple 4.17

Assume that 2 kb of data needs to be transferred. One method is that device interrupts the processor, when |
‏بن دي‎ bytes of data are ready and generate the interrupt. The 158 reads the 1 or 4 or 8 bytes and put these
into the memory addresses. Assume that the device generates the interrupt and transfers the 8 bytes. Number of
സട required will be 2 k/8 = 2048/8 = 256 and ISR has to be run 250 times. A DMA is the beter

An 10 program initializes the DMAC for 2 kb burst mode transfer from a memory address for the VO
ഇ an extemal device starting from memory address M,. DMAC loads 2048 in a data count register and
loads M, in address register on initialization.

On an external device requesting the DMA, the DMAC sends HOLD request signal to the processor.
Processor acknowledges by the HLDA (hold acknowledge) signal that when the system buses are not in use.
DMAC transfers the bytes from 1/0 bus to the memory bus in burst from 10 bus to the 1 bus
7 lines and keeps track of the data counts in the DC (data count) register. Transfer takes place to

addresses from M, to M, + 2047. DC = 0 after the transfer completes.
DMAC imerrupts the processor so that the processor is notified at the end of DMA transfer
and an ISR can re-initialize the DMAC for the next transfer.

channels. A multi-channel DMAC provides DMA

A DMAC may also provide memory access to multiple
action from system memories and two (or more 10) devices. There is a separate set of registers for programming
tach channel. There may be the separate or common interrupt signals in the case of multi-channel DMAC.

സം 80x86 processors do not have on-chip DMAC units. The 8051 family member 83C152JA (and its
sister JB, JC and JD versions) have two DMA channels on-chip. The 80196KC has a PTS (peripheral
tansactions server) that supports DMA functions. (Only single and bulk transfer modes are supported, not
the burst transfer mode.) The MC68340 microcontroller has two on-chip DMA channels. 80960CA has four-
channel DMAC on chip, with ೩ mode called demand transfer mode also provided.

between memory and /O devices compared
Jement and uses the system buses as and

DMAC in sophisticated systems so that
and to the

‎ak transfers‏ اک سا ا یا ہش
‎when -driven data transfer as that has in-built processing ೮‏
‎made available by the processor. Designers can use pret‏ اسه ‎the‏
‎Peripherals. performance improves by separate processing of bulk ೧೯ burst dats (257 m‏