fnd out which exception caused the processor to interrupt and divert the program. Such a mechanism in

processor architecture results in provisioning for the unlimited number of exception handling routines
in the system all having the common interrupt vector address. Figure 4.6(c) shows the ISR VECTADDR
with common vector address for all exceptions, traps and signals resulting from SWI. 1

417000 of Interrupt Sources having Common Vector Address =^ source group in the hardware
may have the same ISR_VECTADDR.

007101 4.9

Consider 8051, TI (transmitter interrupt) and RI (receiver interrupt) are the sources in the same group
having identical ISR_VECTADDR. पा is an interrupt that is generated when the serial buffer register for
sransmission completes serial transmission, and RI is when the buffer receives a byte from the serial receiver.
[SR at the ISR_ADDR to which the program jumps or which is called from bytes at the ISR_ ‏0ی۷۲‎ 1
most first identify the interrupt source (whether TI or RI) in case of the identical vector address or ISR
address for a group of sources. Identification is from a flag in the status register. Setting of a specific

satus flag in the device flag register enables identification of the interrupt source in the group by

the ISR that runs after vectoring.

There are two types of handling mechanisms in processor hardware. The processor-handling mechanism
provides for fetching into the PC either (i) the ISR instruction at the ISR_VECTADDR or (ii) the ISR address
from the bytes at the ISR_VECTADDR.

1. There are some processors, which use ISR_VECTADDR directly as ISR address and the processor
fetches the ISR instruction from there, for example, ARM or 8051. The ARM permits the use of
4-byte instruction for the jump to the ISR (routine for the interrupt servicing). Figure 4.7(a) shows the
use of ISR_ VECTADDR in ARM for the jump to the routine for the interrupt servicing. The 8051
microcontroller permits the use of short ISR of maximum 8 bytes for the internal devices. The short
ISR codes can also use a call instruction to call a detailed routine. Figure 4.7(b) and (c) shows the use
of ISR_ VECTADDR in 8051 in case of short-code and long-code ISR, respectively.

2. There are some processors, which use ISR_VECTADDR indirectly as ISR address and the processor
fetches the ISR address from the bytes saved at the ISR_VECTADDR, for example, 80x86.
Figure 4.7(d) shows the use of ISR_ VECTADDR address in 8086. Processor of interrupt of type n
vectors to address 0x00004 x n and fetches 16 bits for sending into IP (instruction pointer register)
and another 16 bits for sending into CS (code segment register) The ISR for interrupt will execute
from address 0x100000 % CS + IP.

വ; Vector Table System software designer must provide for specifying the bytes at each
ISR First ⋅ ADDR address. The bytes are for either ISR short code [Figure 4.7(b)] or jump instruction to the
fetchin Pe pe (Figure 4.7(a)] or ISR short code with call to the full code of the ISR [Figure 4.7(c)] or for

۸ ‏دو‎ for finding the ISR address [Figure 4.7(8)]. ۱ ۱ ۱
lable has acilitates the service of the multiple interrupting sources for each internal device. Each row 0
an ISR_VECTADDR and the bytes are saved at each ISR_VECTADDR. Vector table location 10 the
681101) Piney 0௩ the processor. It is located at the higher memory addresses, OxFFCO to OxFFFB in
lowest memory 15 at the lowest memory addresses 0x00000 ம 077 in 80x86 processor. It starts from 5
Multiple ‏ز‎ addresses 000000000 in ARM7. Figure 4.8 shows a vector table in the memory in case ©

31೮701 sources or source groups.