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10000CS405122101

Explain memory hierarchy.
Consider the design of a three level memory hierarchy with the following

specifications for memory characteristics:

| Memory Level | Access time Capacity | Cost/Kbyte
Cache tl = 25 ns 51 = 512 Kbytes | ೮1 = $1.25
Main memory t2 = 905 ns 52 = 32 Mbytes | C2 = $0.24

Disk array 13 = 4175 93 = 39 Gbytes C3 = $0.0002

Hit ratio of cache memory 15 h1=0.98 and a hit ratio of main memory 15 h2=0.9.
(i) Calculate the effective access time.
(11) Calculate the total memory cost.
Explain Flynn’s classification of computer architecture with diagrams.
Explain the inclusion, coherence and locality of reference properties of memory
hierarchy.
PART C

Answer any two full questions, each carries 9 marks.
Design an 8 input omega network using 2X2 switches as building blocks. Show
the switch settings for the permutation 71 = (0,6,4,7,3)(1,5)(2). Show the
conflicts in switch settings, if any. Explain blocking and non-blocking networks
in this context.
Explain the significance of multiport memory.
Consider the three-stage pipelined processor specified by the following

reservation table and answer the following: (S indicate the stages)

1. List the set of forbidden latencies and the collision vector.
2. Draw the state transition diagram showing all possible initial sequences

without causing a collision in the pipeline.

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