Semester : SEMESTER 3
Subject : Logic Circuit Design
Year : 2019
Term : DECEMBER
Scheme : 2015 Full Time
Course Code : EC 207
Page:3
E C192056 Pages:3
9 a) Design a mealy machine to detect an input sequencel!0110. The system should be (10)
able to detect overlapped sequence. Also draw the state diagram
b) Obtain a minimum row primitive flow table for the state table shown below. (10)
५0० | & | ~~ | तो | ली | +| ५५ | | غم
10
11
12
13
14
oR मैप मैप بد
Page 3 of 3