Semester : SEMESTER 4
Subject : Digital Electronics and Logic Design
Year : 2020
Term : SEPTEMBER
Scheme : 2015 Full Time
Course Code : EE 204
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02000EE204052003
PART (^
Answer any two questions, each carries 10 marks
Develop a 3-stage carry look ahead adder and implement using basic gates.
Realize the following function F(A,B,C,D) = )m(1,3,4,10,11,12,13) using
(i) 4X 1 MUX (ii) 8۶۱۸10۸5
Explain a 3 bit asynchronous up counter. Draw the timing diagram and truth
table.
Draw the logic diagram of J-K flip flop and explain it. What is the advantage of
J-K flip flop over S-R flip flop.
PART D
Answer any two questions, each carries 10 marks
Design a 3-bit gray code synchronous counter using J-K flip flop and explain
the steps in detail.
Compare Mealy and Moore state machine models with example.
Differentiate between ROM and RAM.
Implement a full adder circuit using VHDL
Explain the working of successive approximation ADC. Mention the advantages
and disadvantages.
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