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00000CS405 121902

i) What are the forbidden latencies?

ii) Draw the transition diagram.

iii) List all the simple cycles and greedy cycles.

iv) Determine the optimal constant latency cycle and minimal average latency
(MAL).

v) Let the pipeline clock period be t=10ns. Determine the throughput of the

pipeline.

Compare full map directories with limited directories.

Explain E-cube routing. Consider a 64 -node hypercube network. Based on E-

cube routing algorithm, show how to route a message from 101101 to 011010.

Find all intermediate nodes on routing path.

PART D
Answer any two full questions, each carries 12 marks.

Explain the importance of Tomasulo’s algorithm for dynamic instruction
scheduling.

Describe the various mechanisms for improving the performance of instruction
pipeline.

Explain various latency hiding techniques.

Differentiate between static and dynamic data flow computers.

Explain various branch prediction techniques.

With suitable diagrams explain ETL/EM-4 architecture.

aK

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