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00000CS405 121902

Consider the design of a three-level memory hierarchy with the following

specifications for memory characteristics:

Memory Access Capacity Cost/Kbyte

Level time

Cache tl=20ns s1=512Kbytes ௦1-$1.30
Main Memory | t2=905ns_ | s2=32Mbytes c2=$0.2
Disk array s3=40Gbytes ௦3-$0.0003

Hit ratio of cache memory is h1=0.98 and a hit ratio of main memory is h2=0.9.

(i) Calculate the effective access time.
(ii) Calculate the total memory cost.
State and explain Bernstein’s conditions for parallelism?
Detect parallelism in the following code using Bernstein’s conditions. Assume

there are sufficient numbers of resources available.

Pl: C=D*E

P2: M=G+C
23; A=B+C
P4: C=L+M
25: F=G/E

PART ^
Answer any two full questions, each carries 9 marks.
Design an 8 input omega network using 2X2 switches as building blocks. Show

the switch settings for the permutation 7 1-(0,6,3,2,5)(1,4). Show the conflicts
in switch settings, if any. Explain blocking and non-blocking networks in this
context.

Draw the two state transition graphs for a cache block using write -invalidate
write -through snoopy bus protocol.

With suitable diagram explain different flow control strategies for resolving a
collision between two packets.

Consider the following pipeline reservation table.

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