Semester : SEMESTER 3
Subject : Switching Theory and Logic Design
Year : 2020
Term : SEPTEMBER
Branch : COMPUTER SCIENCE AND ENGINEERING
Scheme : 2015 Full Time
Course Code : CS 203
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00000CS 203121902
Reduce the following expression using K-Map. AB’C+B’+BD’+ABD’+A’C
Perform the following operations
1. (C45A)uex +(4B26)HEx 11. (76)ocr +(23)ocr
Simplify the Boolean function F (w, x, 9, 2) = Xm(0,5,7,8,9, 10, 11, 14, 15)
using Quine-McCluskey method.
PART C
Answer all questions, each carries 3 marks.
Differentiate combinational and sequential circuits. Give one example for each.
Implement the Exclusive OR operation using NAND gates only.
Give the truth table, characteristics table, excitation table and characteristic
equation of SR flip-flop.
Explain state table and state diagram with an example.
PART D
Answer any two full questions, each carries9 marks.
What is the disadvantage of binary parallel adder? Explain how a look ahead
adder speeds up the addition process. Clearly show the derivations of equations.
Explain race around condition in JK flip-flop. Explain how a master slave flip
flop avoids race around condition.
Compare the working of edge-triggered flip flop and level-triggered flip flop.
Design a code converter for converting BCD to Excess 3 code.
Explain the procedure to convert JK flip flop into T flip flop.
PART 17
Answer any four full questions, each carries 10 marks.
Design and implement a 4 bit binary synchronous down counter.
Draw and explain 4 bit Johnson counter with its timing sequence.
Implement a 4- bit bidirectional shift register with parallel load.
With a block diagram, explain the use of shift registers for serial transfer of data.
Describe the working of Programmable Logic Array (PLA) with ೩ block
diagram and a simple example.
Write notes on Read Only Memory(ROM) and give any 2 applications of ROM.
Write notes on Random Access Memory.
Draw a flow chart and explain the addition / subtraction of two floating point
numbers.
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