( 00000EE203121901 Pages: 2

Reg No.: Name:
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

Third semester B.Tech examinations (S) September 2020

Course Code: EE203
Course Name: ANALOG ELECTRONICS CIRCUITS

Max. Marks: 100 Duration: 3 Hours
PARTA
Answer all questions, each carries 5 marks. Marks
1 Sketch the circuit of a biased positive clamper with a biasing voltage of +2۷ for (5)

a +10V square wave input. Also plot its output voltage waveform and explain
its operation.
2 State and explain Miller’s theorem. (5)
3 An amplifier having an input resistance 4kQ has a voltage gain of 200. If a (5)
series negative feedback with B=0.01 is introduced, determine the value of input
resistance of the feedback amplifier. If the amplifier in its open loop
configuration had cut off frequencies fj= 2kHz and {= 500kHz before the

feedback path was added, what is the new bandwidth of the circuit?

4 Why op-amp is not used in open loop for most of the applications? (5)
5 Deduce the expression for closed loop voltage gain of non-inverting amplifier. (5)
6 Explain the operation of an op-amp comparator with circuit diagram and (5)
waveforms
7 Explain the operation of op-amp based crystal oscillator. Mention its advantage. (5)
8 Design a Wien Bridge oscillator circuit using op-amp having an oscillating (5)
frequency of 10kHz.
PART B

Answer any two full questions, each carries 10 marks.
9 ஐ Explain the operation of a two level clipper circuit. (5)
b) Determine the minimum and maximum possible values of series resistance Rs (5)
of a zener voltage regulator circuit feeding a 1kQ load from a supply voltage of
20V. Maximum value of zener current is 40mA and zener voltage is 10V.

10 a) With the help of a neat diagram, explain the small signal model of FET. (4)

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