Semester : SEMESTER 5
Subject : Digital System Design
Year : 2019
Term : MAY
Scheme : 2015 Full Time
Course Code : EC 361
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E1223 Pages: 3
(Note: ‘indicates complement).
Describe the Fault Table method used for effective test set generation for the
circuit whose logic equation is f= (a.b)’ + b.d’
Explain different test pattern generation for BIST.
PART ட
Answer any two full questions, each carries 20 marks.
Implement the following functions using PLA and obtain their compatibility
matrix.
11(೩,0,0,6) = 2 (1,2,3,4,5,6,8,10,13,15)
f2(a,b,c,d) = » (2,9,10,12,14, 15)
Explain different kinds of PLA folding
What are FPGAs? What are the differences between CPLD and FPGA? What are
the advantages of FPGA?
Explain the architecture of XC 4000 FPGA family.
Using suitable illustrations explain the XC4000 programmable interconnect.
Obtain the compatibility matrix for implementing the following functions:
Z1(x1,x2,x3) ടാലി
22(x1,x2,x3) = 1.2: + 2ح
Z3(x1,x2,x3) = x2’.x3 + x2.x3’
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