Semester : SEMESTER 1
Subject : Advanced Signal Processing
Year : 2018
Term : DECEMBER
Branch : POWER CONTROL AND DRIVES
Scheme : 2015 Full Time
Course Code : 01 EE 6503
Page:3
9.
a. Briefly explain the multistage implementation of sampling rate conversion
(4 marks)
b. Briefly explain the direct form FIR filter structure with efficient implementation of
Decimator & Interpolator. (8 marks)