Write the difference in how stores are handled in a speculative processor [21 versus
in Tomosulo's approach.

What are the different steps involved in instruction execution in a system [4) which
supports hardware based speculation

a.Describe the Intel core i7 pipeline structure.

0.

6.

Show how the following code sequence lays out in convoys, assuming a single [3]
copy of each vector functional unit. How many chimes will this vector sequence
take?

LV VI,Rx vector X
MULVS.D 72൨20 = ;vector-scalar multiply
LV V3,Ry
ADDVV.D V4,V2,V3 add two vectors V4,Ry

;store the sum
What do you understand by flexible chaining in vector processing?

a. Vi'hat are the two different approaches used to issue multiple instructions per [3]
clock in a dynamically scheduled processor?

b.

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The largest configuration of a Cray 790 has 32 processors, each capable of [3]
generating 4 loads and 2 stores per clock cycle. The processor clock cycle is 2.167 ns,
while the cycle time of the SRAMs used inthe memory system is 15 ns. Calculate the
minimum number of memory banks required to allow all processors to run at full
memory bandwidth.

Explain the C-Access vector memory scheme. [31

PART C

. Explain the concept of multipart memory organization for a multiprocessor|>]

system.
What do you understand by hierarchical bus system?
Draw an 8x8 Omega network built with 2x2 switches. Check whether the [5]

permutation 9,6,4,7,3)(1,5)(2) is blocking or non-blocking. Explain the routing of a
message from 111 to 011.

a. What is multiprocessor cache coherence? Point out the reasons which cause 9/6
cache inconsistencies.

b.

Assume that words xl and x2 are in the same cache block, which is in the [6] shared
state in the caches of both PI and P2. Assuming the following sequence of events,
identify each miss as a true sharing miss, a false sharing miss, or a hit. Any miss that

would occur if the block size were one word is designated a true sharing miss.
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