PART 8
a. Write the structure and purpose of reservation stations used with machines [51 that uses
Tomasulo's algorithm.
b, Write notes on pipelining used in Intel core-i7. [4]
a. What are the different steps involved in instruction execution in a system [5] which
supports hardware based speculation?
b. Compare the main characteristics used with five primary approaches in use [4) for
multiple -issue processors. http:/hxww.ktuonline.com
a. With a diagram explain about different vector-access memory schemes.
b. Suppose we have 8 memory banks with a bank busy time of 6 clocks and a [3] total
memory latency of 12 cycles. How long will it take to complete a 128element vector
load with a stride of 1? With a stride of 32?

PART 0

a. Explain the concept of multiport memory organization for a multiprocessor [5]
system.
b. What do you understand by hierarchical bus system?

C. Check whether the permutation 0,6,4,7,3) (1,5) (2) ina Omega network built with
2x2 switches is a blocking or non-bloking. Explain the routing of a message
from 001 to 101.

a. Explain different snoopy bus protocols.

b. Assume that words xl and x2 are in the same cache block, which is in the shared state
in the caches of both PI and P2. Assuming the following sequence of events, identify
each miss as a true sharing miss, a false sharing miss, or a hit. Any miss that would
occur if the block size were one word is designated a true sharingmiss.

Time 71 72

1 Write xl
2 Read x2
3 Write x1
4 Write x2
5 Read x2
a. Draw and explain the basic structures of centralized shared-memory [6]

architecture and distributed memory architecture.

b. Draw the state transition diagram of a write invalidate cache coherence [6] protocol
for a private write back cache. Explain about different states and state transitions.