instructions, A hit takes 1 clock cycle and miss penalty is TOO clock cycles)A load or
store hit takes extra clock cycle ona unified cache if there is only | cache port to satisfy
2 simultaneous requests. What is the average access time in each case? Assume write
through cache with a write buffer and ignore stalls due to write buffer. Misses/1000
instructions for instruction, data & unified cache of different size are given below. The
percentage of instruction references is about 74 9/0 .

Size Instructio Data Unified
n Cache Cache cache

16KB 3.82 409 = | 51.0

32 KB 1.36 38.4 43.3

b. Write an assembly language program to implement y(n) = x(n) * h(n)

(6)