Semester : SEMESTER 6
Subject : Embedded System
Year : 2018
Term : MARCH
Scheme : 2015 Full Time
Course Code : EC 308
Page:24
Computer system PCI
٠ When the I/O devices in the distributed embedded subsystems are networked all can
communicate through a common parallel bus.
* PCI connects at high speed to other subsystems having a range of I/O devices at very short
distances (<25 cm) using a parallel bus without having to implement specific interface for
each I/O device.
PCI bus Applications Connects
_ display monitor,
_ printer,
_ character devices.
PCI Bus Feature
_ 32- bit data bus extendible to 64 bits.
_ PCI protocol specifies the ways of interaction between the different components of a
computer.
_A specification version 2.1-synchronous/asynchronous throughput is up to 132/ 528 MB/s
[33M
x 4/ 66Mx 8 Byte/s], operates on 3.3۷ to 5Vsignals.
_ PCI driver can access the hardware automatically as well as by the programmer assigned
addresses.
_ Automatically detects the interfacing systems and assigns new addresses
_ Thus, simplified addition and deletion(attachment and detachment) of the system
peripherals.
FIFO in PCI device/card
_ Each device may use a FIFO controller with a FIFO buffer for maximum throughput.
Identification Numbers
_ A device identifies its address space by three identification numbers, (i) I/O port (11)
Memory locations and (iii) Configuration registers of total 256Bwith a four 4-byte unique
ID. Each PCI device has address space allocation of256 bytes to access it by the host
Computer
PCI device identification
_A sixteen16-bit register in a PCI device identifies this number to let that device auto- detect
it.
_ Another sixteen16-bit register identifies a device ID number. These two numbers let allow
the device to carry out its auto-detection by its host computer.